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A low cost and fast controller architecture for multimedia data storage and retrieval to flash-based storage device

EURASIP journal on embedded systems, 2016-11, Vol.2016 (1), p.1, Article 24 [Peer Reviewed Journal]

The Author(s) 2016 ;EURASIP Journal on Embedded Systems is a copyright of Springer, 2016. ;ISSN: 1687-3963 ;ISSN: 1687-3955 ;EISSN: 1687-3963 ;DOI: 10.1186/s13639-016-0060-8

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  • Title:
    A low cost and fast controller architecture for multimedia data storage and retrieval to flash-based storage device
  • Author: Banerjee, Samiran ; Mukhopadhyay, Sumitra
  • Subjects: Circuits and Systems ; Control Structures and Microprogramming ; Electronic Circuits and Devices ; Engineering ; Signal,Image and Speech Processing
  • Is Part Of: EURASIP journal on embedded systems, 2016-11, Vol.2016 (1), p.1, Article 24
  • Description: Real-time multimedia data access plays an important role in electronic systems; as time goes by, with decrease in data processing speed and increase in communication time, storage time, and retrieval time, the overall response time increases for real-time applications. Therefore, in this paper, a novel real-time, fast, low-cost, system-on-chip (SoC) controller has been proposed and implemented where large volume of data can be efficiently stored and retrieved from flash memory cards. It is being implemented only using hardware description language (HDL) on a field programmable gate array (FPGA) chip without using any other on-board or external hardware resources or high-level languages. The entire controller architecture, in a single chip, contains five different modules and is designed using finite state machine (FSM)-based approach. The modules are card initialization module (CINM), idle module (IM), card read module (CRM), card write module (CWM), and decision module (DM). The architecture is completely synthesized for Spartan 3E xc3s500e-4-fg320 FPGA with only 5% of the total logic utilization. The experimental results tested for microSD, SD, and SDHC cards of different size, and these show that the architecture uses less hardware and clock cycles for card initialization and single/multiblock read/write procedure.
  • Publisher: Cham: Springer International Publishing
  • Language: English
  • Identifier: ISSN: 1687-3963
    ISSN: 1687-3955
    EISSN: 1687-3963
    DOI: 10.1186/s13639-016-0060-8
  • Source: SpringerOpen
    ROAD: Directory of Open Access Scholarly Resources
    ProQuest Central
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