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High-speed CMOS Frequency Divider with Inductive Peaking Technique

Transactions on Electrical and Electronic Materials, 2014, 15(6), , pp.309-314 [Peer Reviewed Journal]

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Title:
High-speed CMOS Frequency Divider with Inductive Peaking Technique
Author: Park, Jung-Woong ; Ahn, Se-Hyuk ; Jeong, Hye-Im ; Kim, Nam-Soo
Subjects: 전기공학
Is Part Of: Transactions on Electrical and Electronic Materials, 2014, 15(6), , pp.309-314
Description: This work proposes an integrated high frequency divider with an inductive peaking technique implemented in a current mode logic (CML) frequency divider. The proposed divider is composed with a master-slave flip-flop, and the master-slave flip-flop acts as a latch and read circuits which have the differential pair and cross-coupled n-MOSFETs. The cascode bias is applied in an inductive peaking circuit as a current source and the cascode bias is used for its high current driving capability and stable frequency response. The proposed divider is designed with $0.18-{\mu}m$ CMOS process, and the simulation used to evaluate the divider is performed with phase-locked loop (PLL) circuit as a feedback circuit. A divide-by-two operation is properly performed at a high frequency of 20 GHz. In the output frequency spectrum of the PLL, a peak frequency of 2 GHz is obtained witha divide-by-eight circuit at an input frequency of 250 MHz. The reference spur is obtained at -64 dBc and the power consumption is 13 mW.
Publisher: 한국전기전자재료학회
Language: English;Korean
Identifier: ISSN: 1229-7607
EISSN: 2092-7592
DOI: 10.4313/TEEM.2014.15.6.309
Source: Alma/SFX Local Collection

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