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Multifrequency signal receivers

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  • Title:
    Multifrequency signal receivers
  • Subjects: ELECTRIC COMMUNICATION TECHNIQUE ; ELECTRICITY ; SELECTING
  • Description: 1,025,216. V.F. receivers. AUTOMATIC ELECTRIC LABORATORIES Inc. April 20, 1964 [Oct. 24, 1963; Oct. 25, 1963], No. 16238/64. Headings H4K and H4R. In a receiver for detecting tone signal bursts in which each burst comprises a number of frequency components each from a separate frequency group, each signal burst is separated into its component frequencies and applied to a detector circuit. The output of the detector circuit is applied to a timing device arranged to time a first time interval and a second time interval. An incoming signal duration must exceed the first time interval before being recognized as a valid signal and an interruption in one or more of the signals has to exceed the second time interval before the interruption is recognized as an intersignal interval. Two embodiments are described, in one of which all the signals have to cease before the second timing interval commences. Fig. 1 shows a receiver in which the tone signal bursts from subscriber 11 cause the generation of an output on a respective one detector from each of the groups of detectors L1 to L4 and H1 to H4, depending on the code combination. On seizure of the processor 50 a signal is applied over lead ST to flip-flop EN to provide an input to AND gate 40. If a signal is present in both a high group of detectors H1 to H4 and a low group L1 to L4 OR gates 38 and 39 supply further inputs to AND gate 40 to initiate the operation of the signal timer 42. At the end of the first predetermined time the timer 42 produces an output signal which via differentiator 43 enables AND gates 18 to 25 to allow the appropriate signal combination to be passed from the detectors 17 to the processor 50 via the flip-flops 26 to 33. An output on one of the flip-flops 26 to 29 operates, via OR gate 36, the flip-flop 35 which conditions the processor 50 to deal with the received signal, and also, via gate 36, resets EN flip-flop 37 to remove an enabling input from AND gate 40. The signal timer output, however, is also fed via AND gate 46 to interdigital timer 47 which does not immediately start timing but furnished an output, via inverter 49, to OR gate 41 to keep signal timer 42 " timed out " even though the signal from gate 40 has ceased. If the processor 50, after evaluating the received signals, finds that no further digits are required the line RST is marked, flip-flop 35 reset, which resets those of flip-flops 26 to 33 which have been operated, and the next setting of EN flip-flop 37 is upon trunk seizure. If another digit is required line ST is marked to set EN flip-flop 37, which operates OR gate 34 to reset flip-flops 26 to 33, and enables AND gate 40. When the incoming signal is interrupted OR gates 38 and 39 are disabled, disabling OR gate 45 and AND gate 46 and starting the timing operation of interdigital timer 47. Should no further signal be received before the completion of the timing interval OR gate 41 is disabled so resetting timer 42 making the receiver ready to receive the next digit. If the signal reappears before the end of the interdigital interval the timer 47 will reset and start retiming after the following break in the received signal thus preventing a signal with an interference break in it being registered as two similar digits. Figs. 4 and 5 show some detail circuits of an alternative embodiment which differs from the first embodiment in that, in the first embodiment, all the signals have to be interrupted before the interval timer starts timing and in the alternative embodiment if either signal is interrupted the interval timer commences timing. In addition the alternative embodiment utilizes the same timer circuit to time the duration of a valid signal and the duration of a valid interruption with a modification of the timing circuit time constant to differentiate the two. In this embodiment signals from a high band detector, e.g. HD1, and a low band detector, e.g. LD1, are applied to an AND gate formed by diodes CR8 and CR9 to operate transistor Q6. The collector signal of Q6 unbalances the circuit of transistor Q7 and Q12 and causes transistor Q8 to conduct to make a charging circuit for capacitor C5 via transistors Q12 and Q8, diode CR15, and R27 in parallel with R26 and CR18. After, e.g. 25 millisecs., should the signal not be interrupted, the charge on C5 is sufficient to fire the unijunction transistor Q9 to trigger flip-flop Q10, Q11 which in turn triggers monostable multivibrator Q13 and Q14 to place a negative potential on line EN for the duration of operation of the multivibrator. The potential on line EN operates the high and low group control circuits HDC and LDC which enables transistor Q2 in the detector circuit to allow the signal code to be fed out to the processing equipment. The potential on CR4 is also applied via the control circuit to inhibit all the other detector circuits in the respective group. The operation of the bi-stable circuit Q10, Q11, also causes the rebalancing of the circuit Q7, Q12 and therefore cuts off the charging circuit of capacitor C5 at transistor Q8. Should either, or both, inputs on lines PCH or PCL cease the circuit Q7, Q12, will again be unbalanced, in an opposite direction to the first unbalance, Q8 will again conduct and C5 charge this time through Q7 and since R37 is now at ground potential CR18, is cut off and the charging time constant increased to about 45 m.secs. since charging current can no longer flow in R26 and CR18 which are in parallel with R27. If the interruption lasts for greater than 45 millisecs. Q9 fires restoring the flip-flop Q10 and Q11 to its original condition and rebalancing Q7 and Q12 to cut off Q8 and allow C5 to discharge so that the circuit is ready to receive the following code signal. If the signal reappears before C5 is charged and Q9 fires, C5 is discharged and the interval timing begins again on the next break in the signal applied over lines PCH or PCL.
  • Creation Date: 1966
  • Language: English
  • Source: esp@cenet
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