skip to main content
Language:
Search Limited to: Search Limited to: Resource type Show Results with: Show Results with: Search type Index

High-Resolution Wideband Vector-Sum Digital Phase Shifter With On-Chip Phase Linearity Enhancement Technology

IEEE transactions on circuits and systems. I, Regular papers, 2021-06, Vol.68 (6), p.2457-2469 [Peer Reviewed Journal]

ISSN: 1549-8328 ;EISSN: 1558-0806 ;DOI: 10.1109/TCSI.2021.3063274 ;CODEN: ITCSCH

Digital Resources/Online E-Resources

Citations Cited by
  • Title:
    High-Resolution Wideband Vector-Sum Digital Phase Shifter With On-Chip Phase Linearity Enhancement Technology
  • Author: Zhou, Jie ; Qian, Huizhen Jenny ; Luo, Xun
  • Subjects: Calibration ; Linearity ; low amplitude/phase error ; phase linearity enhancement ; Phase shifter ; Phase shifters ; PVT-insensitive ; System-on-chip ; Topology ; Voltage control ; Wideband
  • Is Part Of: IEEE transactions on circuits and systems. I, Regular papers, 2021-06, Vol.68 (6), p.2457-2469
  • Description: In this paper, a wideband vector-sum phase shifter with phase linearity enhancement technology is proposed to minimize phase error. The digital phase shifter synthesizes the output phases by modulating and summing four quadrature signals. A common-source stage with transformer-based matching network and a quadrature-all-pass filter (QAF) are utilized for the quadrature signals generation within a wideband. Besides, to decrease the influence of parasitics on amplitude and phase error, a resistor-based compensation technology is employed in the QAF implementation. Then, to obtain the 360° range high resolution phase shifts, the quadrature signals are modulated by four Gilbert-type variable gain amplifiers (VGAs) with digital-controlled current-digital to analog converters (current-DACs). To further minimize phase error, an on-chip phase linearity enhancement loop is utilized. The drain voltages of current-DACs are detected and compared to the presupposed reference voltages generated by the loop. Besides, the compared results are fed back to control the current-DACs to achieve phase linearity enhancement. To verify the mentioned mechanism, a 7-bit digital phase shifter operating at 22-44 GHz with on-chip phase linearity enhancement technology is implemented and fabricated in a 28-nm CMOS technology. Based on the phase linearity enhancement technology, the phase shifter exhibits a RMS amplitude error of 0.36-0.59 dB and RMS phase error of 0.92° −1.02° without off-chip digital pre-distortion (DPD) technology. The total DC power consumption including the phase linearity enhancement loops is 35 mW under a 0.9V supply voltage.
  • Publisher: IEEE
  • Language: English
  • Identifier: ISSN: 1549-8328
    EISSN: 1558-0806
    DOI: 10.1109/TCSI.2021.3063274
    CODEN: ITCSCH
  • Source: IEEE Open Access Journals
Back to results list
INSPIRE LIBRARY - TON DUC THANG UNIVERSITY (84-028) 37 755 057 Feedback
19 Nguyen Huu Tho St. Dist.7, HCM thuvien@tdtu.edu.vn

Copyright © 2017 INSPIRE LIBRARY - TON DUC THANG UNIVERSITY

Searching Remote Databases, Please Wait