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A fast on-chip debugging design for RISC-V processor

Journal of physics. Conference series, 2021-07, Vol.1976 (1), p.12056 [Peer Reviewed Journal]

Published under licence by IOP Publishing Ltd ;2021. This work is published under http://creativecommons.org/licenses/by/3.0/ (the “License”). Notwithstanding the ProQuest Terms and Conditions, you may use this content in accordance with the terms of the License. ;ISSN: 1742-6588 ;EISSN: 1742-6596 ;DOI: 10.1088/1742-6596/1976/1/012056

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  • Title:
    A fast on-chip debugging design for RISC-V processor
  • Author: Gao, Shan ; Xiao, Wan’ang ; Yang, Zhenghong ; Wu, Dehua ; Gao, Wanlin
  • Subjects: Debugging ; Microprocessors ; RISC
  • Is Part Of: Journal of physics. Conference series, 2021-07, Vol.1976 (1), p.12056
  • Description: Abstract In order to improve the efficiency of on-chip debugging, a fast on-chip debugging design is proposed, which adopts JTAG interface and is applied in RISC-V processor. In this paper, we extend some debugging instructions, effectively reducing data entry by operating the debugging bus directly, and realize the breakpoint, pause, single step, et al., providing conveniences for the development and debugging of the software system.
  • Publisher: Bristol: IOP Publishing
  • Language: English
  • Identifier: ISSN: 1742-6588
    EISSN: 1742-6596
    DOI: 10.1088/1742-6596/1976/1/012056
  • Source: IOP Publishing Free Content
    AUTh Library subscriptions: ProQuest Central
    IOPscience (Open Access)
    GFMER Free Medical Journals
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