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100-Phase, dual-loop delay-locked loop for impulse radio ultra-wideband coherent receiver synchronisation

IET circuits, devices & systems, 2011-11, Vol.5 (6), p.484-493 [Peer Reviewed Journal]

2015 INIST-CNRS ;ISSN: 1751-858X ;EISSN: 1751-8598 ;DOI: 10.1049/iet-cds.2011.0112

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Title:
100-Phase, dual-loop delay-locked loop for impulse radio ultra-wideband coherent receiver synchronisation
Author: XIA, L ; CHEN, H ; HUANG, Y ; HONG, Z ; CHIANG, P. Y
Subjects: Applied sciences ; Circuit properties ; Circuits of signal characteristics conditioning (including delay circuits) ; Coherence ; Design. Technologies. Operation analysis. Testing ; Dynamic link libraries ; Electric, optical and optoelectronic circuits ; Electronic circuits ; Electronics ; Exact sciences and technology ; Impulses ; Integrated circuits ; Jitter ; Radio ; Receivers ; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices ; Tracking ; Ultrawideband
Is Part Of: IET circuits, devices & systems, 2011-11, Vol.5 (6), p.484-493
Description: Receiver timing synchronisation is a significant challenge for impulse radio ultra-wideband (IR-UWB) systems due to the low received power and narrow pulse width. In a coherent receiver, the local template pulses need to be synchronised with the received pulses with a precision of tens of picoseconds. Because of the periodic reduction in received correlated power, the traditional two-stage synchronisation method (acquisition and tracking) is not suitable for a single-path IR-UWB receiver. A tracking only, dual-loop delay-locked loop (DLL) with a 100 ps minimum phase shift is proposed to overcome this issue. This dual-loop DLL, employing a higher frequency fine loop, exhibits a better jitter transfer characteristic compared with a conventional dual-loop DLL. Measurement results of a 130 nm CMOS prototype indicate a locking frequency range of 30 MHz-120 MHz, and a best output jitter of 5.9 ps-rms (input reference jitter is 2.9 ps-rms). The total power consumption is 1.8 mW with a 1.2 V supply voltage.
Publisher: Stevenage: Institution of Engineering and Technology
Language: English
Identifier: ISSN: 1751-858X
EISSN: 1751-8598
DOI: 10.1049/iet-cds.2011.0112
Source: ProQuest Central

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100-Phase, dual-loop delay-locked loop for impulse radio ultra-wideband coherent receiver synchronisation

2015 INIST-CNRS ;ISSN: 1751-858X ;EISSN: 1751-8598 ;DOI: 10.1049/iet-cds.2011.0112

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